🧠 Operating Systems — Master Interview & Revision Guide (Deep Dive)
Targeted for: Juspay Elimination Round, Hackathon Part B Concurrency Architecture & Systems Engineering Interviews.
Core Focus: Thread-safety invariants, low-level lock implementations, context switching mechanics, memory management, multicore cache coherence, and runtime optimization.
📑 Complete OS Module Index
| # | Document | Core Topics Covered | Juspay High-Yield Relevance |
|---|---|---|---|
| 01 | 01-process-structure-and-lifecycle.md | Virtual Address Space (Text, Data, BSS, Heap, Stack), Stack frames, PCB (task_struct), 5-state process lifecycle, Zombie vs Orphan vs Daemon | ⭐⭐⭐ Foundational memory model and process architecture |
| 02 | 02-process-vs-thread-and-ipc.md | Process vs Thread comparison matrix, Thread lifecycle, 1:1 vs M:N threading, IPC mechanisms (Pipes, Message Queues, Shared Memory, Sockets, Signals), Architectural selection framework | ⭐⭐⭐⭐ Critical for high-concurrency design |
| 03 | 03-context-switching-and-cpu-scheduling.md | Hardware context switch steps, User vs Kernel mode, Direct vs Cache overhead, "Playing music while coding on single-core", FCFS, SRTF, Round Robin, Linux CFS | ⭐⭐⭐⭐ Direct Juspay Part B interview question |
| 04 | 04-synchronization-and-concurrency.md | The 7-Hour Gauntlet: Concurrency & Memory Models, 8 Race Conditions & ABA, Hardware Atomics (TAS/CAS/LL-SC), Mutex/Futex/Spinlock/TicketLock, Shared vs Exclusive (RW locks), Synchronization Strategies (Coarse/Fine/OCC/Lock-Free), Performance Trade-offs (Cache Bouncing, False Sharing, Amdahl's Law) | ⭐⭐⭐⭐⭐ CORE JUSPAY HACKATHON PART B GAUNTLET |
| 05 | 05-deadlocks-and-bankers-algorithm.md | 4 Coffman Conditions, Resource Allocation Graphs (RAG), Prevention via Hierarchical Lock Ordering, Banker's Algorithm (Full Numerical Safety & Request derivation), Detection & Recovery | ⭐⭐⭐⭐ Essential for Tree of Space deadlocks prevention |
| 06 | 06-memory-management-and-virtual-memory.md | Logical vs Physical translation, MMU & TLB (EMAT formula), Multi-level Paging, Page Fault step-by-step handler, Page Replacement (FIFO, LRU, Optimal), Belady's Anomaly, Thrashing | ⭐⭐⭐⭐ Core systems interview topic |
| 07 | 07-multicore-cache-coherence-and-amdahls-law.md | Concurrency vs True Parallelism, L1/L2/L3 cache hierarchies, 64-byte Cache Lines, False Sharing (alignas(64)), MESI Protocol (M, E, S, I states), Amdahl's Law derivation | ⭐⭐⭐⭐ Direct Juspay Part B interview question |
| 08 | 08-compiler-vs-interpreter-and-jit-optimizations.md | AOT vs Pure Interpreter vs JIT, Tiered Compilation (HotSpot C1/C2, V8), 8-layer optimization cascade for repeated function calls (OSR, Inlining, Escape Analysis, SIMD, Branch Prediction) | ⭐⭐⭐⭐ Direct Juspay technical round question |
| 09 | 09-paging-and-segmentation.md | Paging vs Segmentation architecture, Hardware Address Translation Diagrams, Internal vs External Fragmentation, x86 Paged Segmentation, GDT/LDT, Mathematical bit calculations & SIGSEGV triggers | ⭐⭐⭐⭐ Core systems & memory virtualization interview questions |
| 10 | 10-compilation-pipeline-lowlevel-cpu-and-kernel-architecture.md | Full C/C++ compilation pipeline (Preprocessor, Compiler, Assembler, Linker, Loader), Compiler vs Interpreter internals, Why arrays are 0-indexed, Assembly & CPU pipeline trace of addition, Kernel architecture (Ring 0 vs 3, Interrupts, Syscalls), 100-key keyboard matrix multiplexing puzzle | ⭐⭐⭐⭐⭐ Direct Juspay Technical & Systems Interview questions |
⚡ 10-Minute Rapid Pre-Interview Cheat Sheet
1. Process vs Thread Quick Distinctions
- Process: Isolated memory space (Private Code, Data, Heap, Stack). Heavy creation/context switch overhead. Full fault isolation (one crash does not affect others). Communicates via IPC.
- Thread: Shared memory space (Shared Code, Data, Heap; Private Stack & PC/Registers). Lightweight creation/switching. Zero fault isolation (one unhandled segfault crashes entire process). Direct memory access (requires synchronization).
2. The 4 Coffman Conditions for Deadlock
- Mutual Exclusion: Non-shareable resource.
- Hold and Wait: Process holding resources requests additional ones.
- No Preemption: Resources cannot be forcibly revoked.
- Circular Wait: Closed chain of processes waiting on each other ($P_0 \to P_1 \to \dots \to P_0$).
- Prevention Strategy: Eliminate Circular Wait by enforcing a Global Linear Lock Ordering (e.g., in Tree of Space: always acquire locks from Leaf to Root).
3. Mutex vs Binary Semaphore
- Mutex: Has strict ownership. Only the thread that acquired the mutex can unlock it. Supports priority inheritance to eliminate priority inversion.
- Semaphore: An anonymous signaling counter ($P$ /
waitdecrements, $V$ /postincrements). Has no owner; one thread can wait and another can signal.
4. MESI Cache Coherence Protocol
- M (Modified): Dirty, exclusive to this core's L1 cache, must write back to RAM before eviction.
- E (Exclusive): Clean, exclusive to this core's L1 cache, matches RAM.
- S (Shared): Clean, present in multiple cores' L1 caches, read-only.
- I (Invalid): Stale / unusable line. Triggers cache miss.
- False Sharing: Two threads modifying independent variables on the same 64-byte cache line cause continuous invalidations and bus ping-ponging. Fixed via
alignas(64).
5. Page Fault & Virtual Memory
- Page Fault: Hardware interrupt when accessing a page with Valid bit $= 0$.
- Step Sequence: Trap to Kernel $\to$ Verify address $\to$ Allocate physical frame $\to$ Disk I/O Swap read (process sleeps) $\to$ Update Page Table Entry (Valid $= 1$, Frame $= f$) $\to$ Restart faulted instruction.
- Belady's Anomaly: FIFO page replacement can experience more page faults when allocated more memory frames. (LRU and Optimal are immune because they are Stack Algorithms).
6. Amdahl's Law Speedup Formula
$$S = \frac{1}{(1 - p) + \frac{p}{s}} \implies \lim_{s \to \infty} S = \frac{1}{1 - p}$$
- If 25% of code is sequential lock acquisition, maximum theoretical speedup across infinite cores is $\frac{1}{0.25} = 4\times$.
7. Repeated Function Optimization Cascade (Juspay Question)
When a function is executed thousands of times with predictable input:
- JIT Tier Promotion & OSR: Bytecode compiled to native x86-64 machine code and hot-swapped onto execution stack.
- Method Inlining: Call boundary eliminated.
- Escape Analysis: Object allocation on heap avoided; fields scalar-replaced into CPU registers.
- Constant Folding & Loop Unrolling: Arithmetic evaluated at compile time; loop conditions minimized.
- SIMD Vectorization: 8 operations executed per cycle via AVX-256 registers.
- Hardware Branch Prediction & L1i Cache: Branch Target Buffer achieves ~100% accuracy; tight loop stays resident in 32KB L1 instruction cache.
🎯 Spoken Interview Strategy for Juspay
- State the Invariant First: Whenever discussing synchronization, state the exact safety requirement (e.g., "Mutual exclusion without killing parallelism across disjoint subtrees").
- Name the Race Condition Explicitly: Always point out the exact mechanism (e.g., "This suffers from a Check-Then-Act race condition between line 2 and line 3").
- Trace Thread Interleavings on Demand: Use clear time-stamped traces: $T_1$ reads $\to$ Context Switch $\to$ $T_2$ reads $\to$ Lost Update.
- Connect Theory to Tree-of-Space: Relate abstract concepts (Lock Ordering, CAS, False Sharing, MESI protocol) directly to the Juspay Tree of Space implementation.